1. Technical Field
The present disclosure relates to semiconductor devices, and, more particularly, to via electrodes for semiconductor chips and stacked semiconductor chips interconnected by the via electrodes.
2. Discussion of Related Art
As electronic devices become smaller and smaller the use of wire and solder balls are becoming less and less common. In recent years the semiconductor industry has been striving to cost effectively produce reliable electrically connectable stacks of semiconductor wafers while minimizing manufacturing difficulties.
In the manufacturing of integrated circuit (IC) devices, components and metal circuit lines separated by dielectric substrate material, such as silicon oxide, are typically connected through holes or “vias” which have been etched through the dielectric substrate material. The through silicon via (TSV) is cleaned of photoresist and etch residues and then filled with conductive metal to provide an electrical connection from one side of the substrate to the other.
However, one difficulty that can affect interconnect performance and reliability is when the TSVs are not free of cleaning residue prior to being filled. The removal of such cleaning residue, often called “via veils”, can become difficult because of etch chemistries and may involve the costly and delicate use of aggressive wet chemical solvents to insure clean TSVs that provide reliable electrode connection paths when filled. Strides have been made to minimize this difficulty through the use of a dry de-veiling process rather than the aggressive wet solvent process.
Further, wafer stack packaging (WSP) technology using a TSV as a through hole electrode for multiple layer packaging continues to be used in an attempt to reduce package thickness, size and interconnection length between semiconductor chips/dies.
However, because integration density of semiconductor chips is increasing, the diameters of via holes for forming a conventional TSV are getting smaller. Because an aspect ratio of the hole then becomes very high, voids may be developed in the via hole during filling the hole with conductive material for forming TSV electrode. Such voids precipitate the inducing of a connection failure from one side of the chip to the other, or between dies in the stack.
In an attempt to avoid connection failures, U.S. Patent Publication No. 2008/0092378 proposes a method for manufacturing an electroconductive material-filled through hole substrate of which the front side and back side are electrically conductive to each other through an electroconductive material filled into the through holes. An electroconductive base layer is formed on one side of a core substrate having through holes. The through holes are filled with an electroconductive copper material by electroplating using the electroconductive base layer as a seed layer. However, the disclosure does not address the problem of potential voids in TSVs. Holes in the substrate are merely filled and the substrate stripped off and polished until the electroconductive material in the holes is exposed.
In a further attempt to address connections involved in the stacking of semiconductor chips, U.S. Pat. No. 6,809,421 proposes a multichip semiconductor device having a stack of chips each having a semiconductor substrate which has a surface on which circuit components are formed. While providing for metal plugs as electrodes through the respective substrates, the disclosure also does not address the problem of potential voids in TSVs. Holes in the substrate are merely filled and the substrate stripped off and polished until the metal plug is exposed.
Therefore, a need still exists for approaches for providing effective TSVs, particularly those that allow for firm electrical connection between components and circuits separated by dielectric layers, and those that avoid voids in via electrodes that can induce connection failures between one side of a semiconductor chip to the other side, or between chips in a stack of chips.